Tesla has unveiled an updated roadmap for its AI accelerators, shedding light on the company’s future chip development. The next-generation SI6 inference chip is slated to deliver a staggering 80 times the processing power of its predecessor, HW4, while the Dojo D3 training accelerator is set to undergo a significant architectural overhaul.
Shifting Sands: From AI to Super Intelligence
A notable change in Tesla’s nomenclature is the shift from “Artificial Intelligence” (AI) to “Super Intelligence” (SI) for its accelerator series. This rebranding extends to SpaceX’s AI division, which Elon Musk confirmed will now be known as SpaceXSI. This terminology change signals a heightened ambition in the company’s AI endeavors.
The Evolution of Tesla’s AI Accelerators
Tesla’s current and planned chip lineup, now categorized under the SI series, highlights a relentless pursuit of performance gains:
- SI4 / HW4: Currently in mass production, utilizing Samsung’s 7nm process, this chip serves as the performance benchmark for Tesla’s Full Self-Driving (FSD) technology. It’s estimated to offer around 216-576 TOPS, with 16GB of GDDR6 memory.
- SI5 / HW5: Expected to move towards mass production soon, SI5 will adopt a multi-chip module (MCM) design, manufactured on TSMC’s 3nm and Samsung’s 2nm processes. It aims for a 40x performance leap over SI4, potentially reaching 8640-23040 TOPS, with memory capacity expanding to 96GB. Power consumption is projected to be high, between 250W-800W.
- SI6 / HW6: This future inference accelerator, targeted for 2029-2030, is the star of the roadmap, promising 80 times the compute power of SI4 and a 144GB memory capacity. It will likely be manufactured on Samsung’s 2nm process.
Dojo D3: A New Architecture for Training
The Dojo training accelerator is also undergoing a significant transformation. The Dojo D3 will abandon the System-on-Wafer (SoW) architecture that relied heavily on distributed on-chip SRAM, as seen in D1. Instead, D3 will embrace a chiplet-based design utilizing 2.5D and 3D packaging, coupled with stacked High Bandwidth Memory (HBM).
This shift to HBM is crucial for modern AI models that demand vast amounts of memory for parameters, activations, and intermediate computations. While SRAM is fast, its capacity is becoming a bottleneck for increasingly complex models.
The move to HBM allows for easier memory scaling but introduces different trade-offs in latency, bandwidth, packaging, and power consumption. Tesla is seemingly moving away from wafer-level integration for D3, possibly due to cost and complexity concerns associated with large-scale SRAM-centric designs.
Optimized for the Cosmos and Beyond
Intriguingly, Dojo D3 is being optimized for “space, training, and scalability.” This suggests that D3 will not only need to deliver immense computational power but also possess robust extensibility. The specific mention of space deployment hints at the possibility of radiation-hardened variants, indicating a broader application scope than initially anticipated.
SI6: Pushing the Boundaries of Inference
The SI6 inference accelerator represents a monumental leap in performance. Expected to offer 80 times the compute of SI4, its estimated TOPS could range from 17280 to 46080 (17.28-46.08 POPS). This places it in direct, albeit future, competition with offerings from established players like NVIDIA. With a target launch around 2029-2030 and manufactured on Samsung’s 2nm process, the SI6 is set to be a powerhouse for on-device inference.
Tesla has secured a production agreement with Samsung’s foundry division through 2033 for its sixth-generation accelerators. The roadmap suggests SI6 will leverage advanced 2nm process nodes, potentially including performance-enhanced variants with backside power delivery.
While the SI6 continues the MCM design introduced with SI5, the integration of HBM memory for inference chips is not yet explicitly detailed in the roadmap, suggesting it might not be part of the initial SI6 rollout.
The evolution outlined in Tesla’s updated AI accelerator roadmap underscores the company’s deep commitment to in-house chip development, aiming to fuel advancements in autonomous driving and other AI-driven applications.
